Interest in radio frequency integrated circuits (RFICs) for wireless communications in the 2 GHz frequency range has grown tremendously. An analog circuit in front-end transmitters and receivers in RFICs is a mixer that provides signal frequency translation from a radio frequency (RF) to an intermediate frequency (IF) or from an IF to an RF. The mixer usually includes a transconductance stage that converts its input voltage signals to output current signals and a core stage that mixes the output current signals with local oscillator (LO) signals.
Distortion in the transconductance stage is a consideration in the design of the mixer. It is desired to enhance linearity of the transconductance stage to improve linearity of the mixer. In addition to the mixer, other analog circuits, such as low noise amplifiers (LNAs) and filters in a communication system, may also include a transconductance stage. Conventionally the transconductance stage of those analog circuits may be realized with a differential pair circuit that converts its input voltage signals to output current signals. By improving linearity of the transconductance stage, or transconductor, linearity of the mixers, LNAs, and filters in the communication system may be improved.
FIG. 1 illustrates a conventional differential pair circuit 100 that may operate as a transconductor in mixers, LNAs, or filters in a communication system. The differential pair circuit 100 includes a pair of differentially connected metal-oxide-semiconductor (MOS) transistors M1 102 and M2 104. The MOS transistor 102 includes a gate terminal 106, a drain terminal 108, and a source terminal 110. The MOS transistor 104 includes a gate terminal 112, a drain terminal 114, and a source terminal 116. The gate terminal 106 of the MOS transistor M1 102 is coupled to a first input terminal 120 of the differential pair circuit 100. The gate terminal 112 of the MOS transistor M2 104 is coupled to a second input terminal 122 of the differential pair circuit 100. The drain terminal 108 of the MOS transistor M1 102 is coupled to a first output terminal 124 of the differential pair circuit 100. The drain terminal 114 of the MOS transistor M2 104 is coupled to a second output terminal 126 of the differential pair circuit 100. The source terminal 110 of the MOS transistor M1 102 and the source terminal 116 of the MOS transistor M2 104 are connected together to be driven from a constant current source 130. By applying differential voltage signals at the input terminals 120 and 122, differential current signals are output at the output terminals 124 and 126.
In the conventional circuit 100, the MOS transistors M1 102 and M2 104 may have the same length and width, the same threshold voltage, and the same transconductance parameters. Input voltage signals Vi+ 132 and Vi− 134 are applied to the input terminals 120 and 122, respectively. Output current signals IO+ 136 and IO− 138 are provided on the output terminals 124 and 126, respectively. Denoting a differential input voltage as vin which is equal to Vi+−Vi−, a constant current source as ISS 130, and transconductance parameters of the MOS transistors M1 102 and M2 104 as β, a differential output current ΔID, which is equal to IO+-IO−, can be expressed as:
                                          Δ            ⁢                                                  ⁢                          I              D                                =                      β            ·                          v                              i                ⁢                                                                  ⁢                n                                      ·                                                                                2                    ⁢                                                                                  ⁢                                          I                      ss                                                        β                                -                                                      (                                          v                                              i                        ⁢                                                                                                  ⁢                        n                                                              )                                    2                                                                    ,                            Equation        ⁢                                  ⁢                  (          1          )                    when each of the MOS transistors M1 102 and M2 104 operates in a saturation region. As can be seen from Equation (1), within a range in which the differential input voltage vin has a small amplitude, there is approximately provided a linear transfer characteristic such that the output current ΔID varies linearly in relation to the differential input voltage vin. However, when the differential input voltage vin increases to a level in the vicinity of the saturation region, the linearity is lost. As a result, the conventional differential pair circuit 100 may have a relatively narrow input voltage range within which to provide a linear transfer characteristic.
FIG. 2 illustrates a schematic block diagram of a differential signal mixer 200 in accordance with U.S. Pat. No. 7,107,025. The mixer 200 includes an input section 202, a mixing section 204, standby current sources 206 and 208, and tuning components 210 and 212. The input section 202 is operably coupled to receive an input voltage signal 214 and produce therefrom an output current signal 216 in accordance with transconductance properties of the input section 202. The input section 202 includes two current sources 218 and 220, a resistor 222, and two input transistors 224 and 226. Gate terminals of the input transistors 224 and 226 are operably coupled to receive a positive leg of the input voltage 214 and a negative leg of the input voltage 214, respectively. The resistor 222 is operably coupled between source terminals of the input transistors 224 and 226.
FIG. 3 illustrates a linearized transconductance circuit 300 for application in a mixing circuit using a double-balanced cell, in accordance with U.S. Pat. No. 6,542,019. The transconductance circuit 300 includes a first MOS transistor M1 302 and a second MOS transistor M2 304 to create a first balanced pair. Due to a small width-to-length ratio, the first balanced pair exhibits a relatively large linear input range. In addition, the transconductance circuit 300 includes a third MOS transistor M3 306 and a fourth MOS transistor M4 308 to create a second balanced pair. The second balanced pair of the MOS transistors M3 306 and M4 308 have a larger width-to-length ratio than the first balanced pair of the MOS transistors M1 302 and M2 304. This configuration is intended to achieve improved linearity and an improved noise figure.
In addition to linearity, such parameters as gain, noise, or power efficiency, may be important, according to the specific application. However, designing to improve linearity may have a detrimental effect on the other parameters.